System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH		 < data not available > < data not available > < data not available >
Path d:\Xilinx\14.2\ISE_DS\ISE\\lib\nt;
d:\Xilinx\14.2\ISE_DS\ISE\\bin\nt;
D:\Xilinx\14.2\ISE_DS\ISE\bin\nt;
D:\Xilinx\14.2\ISE_DS\ISE\lib\nt;
D:\Xilinx\Vivado\2012.2\bin;
D:\Xilinx\14.2\ISE_DS\PlanAhead\bin;
D:\Xilinx\14.2\ISE_DS\EDK\bin\nt;
D:\Xilinx\14.2\ISE_DS\EDK\lib\nt;
D:\Xilinx\14.2\ISE_DS\EDK\gnu\microblaze\nt\bin;
D:\Xilinx\14.2\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
D:\Xilinx\14.2\ISE_DS\EDK\gnuwin\bin;
D:\Xilinx\14.2\ISE_DS\EDK\gnu\arm\nt\bin;
D:\Xilinx\14.2\ISE_DS\common\bin\nt;
D:\Xilinx\14.2\ISE_DS\common\lib\nt;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\Program Files\Java\jdk1.7.0_13\bin;
c:\Python27		 < data not available > < data not available > < data not available >
XILINX d:\Xilinx\14.2\ISE_DS\ISE\ < data not available > < data not available > < data not available >
XILINX_DSP D:\Xilinx\14.2\ISE_DS\ISE < data not available > < data not available > < data not available >
XILINX_EDK D:\Xilinx\14.2\ISE_DS\EDK < data not available > < data not available > < data not available >
XILINX_PLANAHEAD D:\Xilinx\14.2\ISE_DS\PlanAhead < data not available > < data not available > < data not available >
XILINX_VIVADO D:\Xilinx\Vivado\2012.2 < data not available > < data not available > < data not available >
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   m25pe10_io.prj  
-ofn   m25pe10_io  
-ofmt   NGC NGC
-p   xc6slx16-2-csg225  
-top   m25pe10_io  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 1 1
-power Power Reduction NO No
-iuc Use synthesis Constraints File NO No
-keep_hierarchy Keep Hierarchy No No
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes No
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES Yes
-sd Cores Search Directories {"ipcore_dir" }  
-write_timing_constraints Write Timing Constraints NO No
-cross_clock_analysis Cross Clock Analysis NO No
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100
-bram_utilization_ratio BRAM Utilization Ratio 100 100
-dsp_utilization_ratio DSP Utilization Ratio 100 100
-reduce_control_sets   Auto Auto
-fsm_extract   YES Yes
-fsm_encoding   Auto Auto
-safe_implementation   No No
-fsm_style   LUT LUT
-ram_extract   Yes Yes
-ram_style   Auto Auto
-rom_extract   Yes Yes
-shreg_extract   YES Yes
-rom_style   Auto Auto
-auto_bram_packing   NO No
-resource_sharing   YES Yes
-async_to_sync   NO No
-use_dsp48   Auto Auto
-iobuf   YES Yes
-max_fanout   100000 100000
-bufg   16 16
-register_duplication   YES Yes
-register_balancing   No No
-optimize_primitives   NO No
-use_clock_enable   Auto Auto
-use_sync_set   Auto Auto
-use_sync_reset   Auto Auto
-iob   Auto Auto
-equivalent_register_removal   YES Yes
-slice_utilization_ratio_maxmargin   5 0
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM) i5-3427U CPU @ 1.80GHz/2293 MHz <  data not available  > <  data not available  > <  data not available  >
Host vgrenache <  data not available  > <  data not available  > <  data not available  >
OS Name Microsoft Windows XP Professional <  data not available  > <  data not available  > <  data not available  >
OS Release Service Pack 3 (build 2600) <  data not available  > <  data not available  > <  data not available  >